OV518 Registers:

Here are some of the most important things that need to be added to this list:
Colors:
Image Processing Control

Register
 R/W
 Description
 Default Value
00h-1Fh
 -
 Probably unused
 Starts at 0xFF, decreases to 0x06
20h (R?)W Input Format Control (undocumented):
Bit 7: Unused? No apparent effect.
Bit 6: Unknown (OV518+ Windows driver sets this). No apparent effect .
Bit 5: Unknown, affects image/compression format. ph[7], bit 4 -> 0
Bit 4: Unknown, affects image/compression format. ph[6], bit 0 -> 1
Bit 3: 1: Enable 8-bit YVYU/GRGB input format. 0: Enable 16-bit YUV/GBR 4:2:2 input format. ph[6], bit 3 -> 1
Bit 2: "Adjust YUV". Enables UV channel and disables Y. It is not known what data is in the UV channels.
Bit 1: "Reverse UV". No apparent effect.
Bit 0: Appears to decimate Y data. Low pass filter? Effect on UV is unknown.		 0x00
21h (R?)W Undocumented (related to frame rate control). Appears to be related to reg 71h. Only used with OV518+? 0x10
22h (R?)W Undocumented (related to frame rate control, probably frame drop) 0x18
23h (R?)W Undocumented (related to frame rate control, probably frame drop) 0xFF
24h (R?)W* Undocumented mode initialization function; dependent on sensor resolution (decimation?) 0x00
25h (R?)W Undocumented mode initialization function; dependent on sensor resolution (decimation?) 0x00
26h
(Has snapshot function) 0x00
27h
(Has snapshot function) 0x00


Down-sample / Clamp / Window

Register
 R/W
 Description
 Default Value
28h
 RW*
 Down-sampling Control:
Bit 7~6: (ph[6], bit 6 and 5)
  • 00: Output 4:0:0 data (8-bit)
  • 01: Output 4:2:0 data (12-bit)
  • 10: Output 4:2:0 data (12-bit)
  • 11: Output 4:2:2 data (16-bit)
Bit 5~4: No apparent function, but appear to be related to bits 6 and 7 (Windows driver uses mask of 0xf0 when setting output)
Bit 3~0: Setting this to >0 enables manual quantization level control. Higher => more quantization. Disables dynamic quantization tables in data stream. ph[6], bit 4 -> 0
 0xC0
29h
 RW*
 Horizontal Segments
Bit 5~0: width / 16
 0x16
2Ah
 RW*
 Vertical Segments
Bit 7~0: height / 4
 0x48
2Bh
 RW*
 Horizontal Offset High
Bit 1~0: Upper 2 bits of X offset (relative to HREF pulse)		 0x00
2Ch
 RW*
 Horizontal Offset Low
Bit 7~0: Lower 8 bits of X offset (relative to HREF pulse) 		0x00
2Dh
 RW*
 Vertical Offset High
Bit 1~0: Upper 2 bits of Y offset (relative to VSYNC pulse)
 0x00
2Eh
 RW*
 Vertical Offset Low
Bit 7~0: Lower 8 bits of Y offset (relative to VSYNC pulse)
 0x00
2Fh
 W
 One Shot Register
Bit 7: Changes to the registers marked with '*' in the R/W column won't take effect until this bit is set. Change takes place during vblank interval. Bit resets to 0 afterward.
 0x00


ISO FIFO and Snapshot Control

Register
 R/W
 Bytes
 Description
 Default Value
30h
 W
 2
 USB isochronous packet size. Must match the current alternate selection. Optional packet number byte is not counted in size.
 0x80
31h
 (R?)W
 1
 ISO Control
(set to 0Fh during init)
 0x02
32h

Undocumented
 0x00
33h
 (R?)W
 1
 Unknown (set to 04h during init)
 0x00
34h - 37h

Undocumented, probably unused 0x00
38h - 3Eh
 same 1
 Same functions as 28h-2Eh, but for snapshot mode
 same
3Fh
 (R?)W
 1
 Bit 7~5: Unused?
Bit 4: Unknown initialization function
Bit 3~0: Unused?
 0x00


I2C (SCCB)

Register
 R/W
 Description
 Default Value
40h
 RW
 I2C Timeout Counter (bits 4~0)
 0x00
41h
 RW
 I2C Slave ID for 2 or 3 byte write cycles (bits 7~0) 0x00
42h
 RW
 I2C Sub-address for 3-byte write cycles (bits 7~0) 0x00
43h
 RW
 I2C Sub-address for 2-byte write cycles (bits 7~0) 0x00
44h
 RW
 I2C Slave ID for 2-byte read cycles (bits 7~0) 0x00
45h
 RW
 I2C Data Port (bits 7~0) ~
46h
 RW
 I2C Clock Prescaler (bits 7~0) 0x00
47h
 R/W
 		I2C Control: (note: bits have different meaning when read)
Bit 7: Unknown function (set after write cycle in some cases)
Bit 4: I2C Abort
Bits 2-1: I2C Transaction Type:
00: 3-Byte write cycle
01: 2-Byte write cycle
1x: 2-Byte read cycle
Bit 0: Launch new I2C bus cycle
 ~
48h
 W
 I2C Snapshot Write Sub-address
 0x00
49h
 W
 I2C Snapshot Data Port
 0x00
4Ah-4Fh
 -
 Probably unused
 0x01


System Control

Register
 R/W
 Description
 Default Value
50h
 RW
 System Reset:
Bit 7: Omitted
Bit 6: Reset registers and state machine (read-only, resets to 0 automatically)
Bit 5: Omitted
Bit 4: Omitted
Bit 3: Omitted
Bit 2: Undocumented, probably not used
Bit 1: Omitted
 Bit 0: Do not set this bit!
 0x00
51h
 RW
 Bit 4~0: Camera clock divisor. Lower == faster frame rate. Zero seems to be an invalid setting.
 0x02
52h
 ->
 Snapshot Control:
Bit 4 (RW): Omitted
Bit 3 (R): Snapshot status
Bit 2 (W): Omitted
Bit 1 (W): Reset snapshot
Bit 0 (RW): Enable snapshot (must set again after every snapshot event)
 0x01
53h
 W
 System Reset and Control:
Bit 7~1: Omitted
Bit 0: Enable system
 0xC0
54h
 RW
 Bits 7~4: Unused
Bits 3~2: GPIO clock ("Debounced Clock") select
00: 375 Hz
01: 750 Hz
10: 1.5 KHz
11: 96 KHz
Bits 1~0: Switching power clock output select
00: 24 KHz
01: 48 KHz
10: 96 KHz
11: 192 KHz		 0x0E
55h
 R
 Bits 7~0: GPIO data inputs
 ~
56h
 RW
 Bits 7~0: GPIO data outputs (LED is usually attached to bit 1)
 0x00
57h
 RW
 Bits 7~0: GPIO IO direction control (0=output, 1=input)
 0xFF
58h
 R
 Bits 7~0: GPIO pulse data inputs
 ~
59h
 W
 Bits 7~0: GPIO pulse clear (0=normal, 1=clear)
 ~
5Ah
 RW
 Bits 7~0: GPIO pulse polarity (0=positive, 1=negative; documentation discrepancy: may be backwards)
 0xFF
5Bh
 RW
 Bits 7~0: GPIO pulse enabled (0=disabled, 1=enabled)
 0x00
5Ch
 RW
 Bits 7~0: GPIO reset mask (0=unmask, 1=mask)
 0x00
5Dh
 RW
 Power-Down Control 0x02
5Eh
 RW
 Bits 7~0: User defined R/W bits
 0x00
5Fh
 R
 Bits 4~0: Revision ID (Connected to revision ID pins)
 ~


(60h-6Fh are unknown)

Register
 R/W
 Description
 Default Value
60h-6Fh
 -
 Probably unused
 0x01


Compression Control ?  (70h-7Fh)

Register
 R/W
 Description
 Default Value
70h

0x10
71h
 R/W
 Unknown (seems to affect quantization when set to 00). Appears to be related to reg 21h. Possibly dynamic quantization range?
0x1E
72h

0x81
73h-7Fh
 -
 Probably unused
 0x01

Quantization Tables   (80h-9Fh)

Register
 R/W
 Description
 Default Value
80-8Fh
 RW
 Y Quantization Table
32 values: first value goes in lower 4 bits of each reg, next value goes in upper 4 bits and so on.
 (multiple values)
90-9Fh
 RW
 UV Quantization Table
32 values: first value goes in lower 4 bits of each reg, next value goes in upper 4 bits and so on.
 (multiple values)

(A0h-BFh are unknown, possibly Huffman table)

(C0h-CFh)

Register
 R/W
 Bytes
 Description
 Default Value (lowest byte only)
C0h


0x87
C1h


0x02
C2h


0x19
C3h


0x0F
C4h
 W
 2
 Unknown (related to memory/ frame rate control)
 0xC8
C5h


0x03
C6h
 W
 2
 Unknown (related to memory/ frame rate control)
 0x7D
C7h
 W
 2
 Unknown (related to memory/ frame rate control)
 0x7D
C8h
 W
 2
 Unknown (related to memory/frame rate control)
 0x72
C9h


0x03
CAh
 W
 3
 Unknown (related to memory/frame rate control)
 0x23
CBh
 W
 2
 Unknown (related to memory/ frame rate control)
 0xEA
CCh
 W
 2
 Unknown (related to memory/ frame rate control)
 0xDC
CDh
 W
 2
 Unknown (related to memory/ frame rate control)
 0x2D
CEh
 W
 2
 Unknown (related to memory/ frame rate control)
 0x53
CFh


0x53

(D0h-FFh are unknown, probably unused)

Register FFh may be related to I2C read

Packet Header:

Byte
 Description
 Controlling Register
0
 Always 0?
 N/A
1
 Always 0?
 N/A
2
 Always 0?
 N/A
3
 Always 0?
 N/A
4
 Bits 7~2: Unknown (Always 0?)
Bits 1~0: Unknown (Usually 10 or 11)
 N/A?
5
 Always 0?
 N/A
6
 Bit 7: Unknown (Always 0?)
Bit 6~5: Output format
Bit 4: Dynamic quantization
Bit 3: 8-bit YVYU/GRGB input format
Bit 2: Unknown (Always 1?)
Bit 1: Odd/Even field?
Bit 0: Unknown
 Unknown
Reg 0x28, Bit 7~6
Reg 0x28, ~Bits 3~0
Reg 0x20, Bit 3
Unknown
Reg 0x46, Bit 2?
Reg 0x20, Bit 4
7
 Bit 7~5: Unknown (Always 1?)
Bit 4: Unknown
Bit 3~0: Frame counter
 Unknown
Reg 0x20, ~Bit 5
Reset by Reg 0x2f?


EOF